Requests for improving the performance of a semiconductor device used in a computer become more and more crucial. Nowadays, there have been extensively used BiCMOS devices combining CMOS devices and bipolar transistors for the purpose of surmounting a speed limit of CMOS devices. High speed operation of BiCMOS devices is greatly influenced by the performance of associated bipolar transistors. It is very important to speed up bipolar transistors in order to improve the performance of BiCMOS devices.
FIGS. 1A to 1C show processes used for explaining the method of manufacturing a bipolar transistor of this type according to a background art, particularly a bipolar transistor of NPN type.
As shown in FIG. 1A, there are first formed within a silicon substrate 1 an N.sup.+ buried layer 2 for leading a collector electrode and a P.sup.+ buried layer 3 for element separation. Next, a silicon epitaxial layer 4 is grown within which an N-well 5 and P-well 6 are formed. Then, a field oxide film 7 is formed by an ordinary selective oxidation method for element separation. Thereafter, ions are implanted to form a deep N.sup.+ diffusion layer 8 and N.sup.++ diffusion layer 9 for leading the collector electrode, and a P.sup.++ diffusion layer 10 for leading a base electrode.
Next, as shown in FIG. 1B, a resist pattern 11 is formed. Using this resist pattern 11 as a mask, boron ions B are implanted as indicated at 12 to introduce base P.sup.- impurities 23 in a base-emitter SDG (source, drain, gate) area and to form a base.
Succeedingly, as shown in FIG. 1C, an SiO.sub.2 film 18A is formed, for example, by a CVD method, and a hole 17A is formed at the area where an emitter is formed. Thereafter, a polysilicon 16 is deposited for forming an emitter by means of an LPCVD method (Low Pressure CVD method). Next, N-type impurities such as arsenic As are introduced within the polysilicon 16. The introduced impurities are diffused into the base-emitter SDG area to form an emitter 17. At the same time, the base P.sup.- impurities are also diffused to form a base (P.sup.-) 15b. Thereafter, an interlayer insulating film 18 such as SiO.sub.2 is formed by a CVD method. Then, an emitter aluminum electrode 19, a base aluminum electrode 20, and collector aluminum electrode 21 are formed, and thereafter a passivation film 22 such as PSG is formed.
The above-described prior art method of forming a bipolar transistor is associated with the following problems with respect to realizing high speed operation. Namely, a bipolar transistor manufactured by the above-described method has a thick base width W.sub.B (refer to FIG. 1C), thereby hindering high speed operation. Such structure results from that the diffusion coefficient of boron B within silicon for forming the base (P.sup.-) 15b is several times as large as that of arsenic As for forming the emitter 17. As well known in the art, how fast a bipolar transistor operates is represented by a cut-off frequency F.sub.T which is inversely proportional to the square of the base width W.sub.B. It is therefore very effective to make thin the base width W.sub.B in order to realize high speed operation of a bipolar transistor. However, the above-described manufacturing method poses a problem of a thick base width W.sub.B.